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74F50109 Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
Product specification IC15 Data Handbook 1990 Sep 14
Philips Semiconductors
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
FEATURE
* Metastable immune characteristics * Output skew guaranteed less than 1.5ns * High source current (IOH = 15mA) ideal for clock driver
applications
PIN CONFIGURATION
RD0 1 16 VCC 15 RD1 14 J1
J0 2 K0 3 CP0 4 SD0 5 Q0 6 Q0 7 GND 8
* Pinout compatible with 74F109 * See 74F5074 for synchronizing dual D-type flip-flop * See 74F50728 for synchronizing cascaded D-type flip-flop * See 74F50729 for synchronizing dual D-type flip-flop with
edge-triggered set and reset TYPE 74F50109 TYPICAL fmax 150MHz TYPICAL SUPPLY CURRENT( TOTAL) 22mA
13 K1 12 CP1 11 SD1 10 Q1 9 Q1
SF00598
LOGIC SYMBOL
2 14 3 13
ORDERING INFORMATION
ORDER CODE COMMERCIAL RANGE DESCRIPTION VCC = 5V 10%, Tamb = 0C to +70C 16-pin plastic DIP 16-pin plastic SO N74F50109N N74F50109D SOT38-4 SOT109-1 PKG DWG #
4 5 1 12 11 15
CP0 J0 SD0 RD0 CP1 SD1 RD1
J1
K0 K1
Q0 Q0 Q1 Q1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS J0, J1 K0, K1 CP0, CP1 SD0, SD1 RD0, RD1 DESCRIPTION J inputs K inputs Clock inputs (active rising edge) Set inputs (active low) Reset inputs (active low) 74F (U.L.) HIGH/ LOW 1.0/0.417 1.0/0.417 1.0/0.033 1.0/0.033 1.0/0.033 LOAD VALUE HIGH/LOW 20A/250A 20A/250A
6 VCC = Pin 16 GND = Pin 8
7
10
9
SF00599
IEC/IEEE SYMBOL
2 1J C1 1K R S 2J C2 2K R S 9 10 7
20A/20A 20A/20A 20A/20A
4 3 1 5 14
6
Q0, Q1, Q0, Q1 Data outputs 750/33 15mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state.
12 13 15 11
SF00600
September 14, 1990
2
853-1388 00422
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
LOGIC DIAGRAM
7, 9 6, 10
Q
Q
device-under-test can be often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build a waveform.0 An experiment was run by continuously operating the devices in the region where metastability will occur. When the device-under-test is a 74F74 (which was not designed with metastable immune characteristics) the waveform will appear as in Fig. 2.
K
3, 13
J CP SD RD
2, 14 4, 12 5, 11 1, 15
Fig. 2 shows clearly that the Q output can vary in time with respect to the Q trigger point. This also implies that the Q or Q output waveshapes may be distorted. This can be verified on an analog scope with a charge plate CRT. Perhaps of even greater interest are the dots running along the 3.5V volt line in the upper right hand quadrant. These show that the Q output did not change state even though the Q output glitched to at least 1.5 volts, the trigger point of the scope. When the device-under-test is a metastable immune part, such as the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q output will appear as in Fig. 3. The 74F5074 Q output will not vary with respect to the Q trigger point even when the a part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flop the only outward manifestation of the event will be an increased clock-to-Q/Q propagation delay. This propagation delay is, of course, a function of the metastability characteristics of the part defined by and T0. The metastability characteristics of the 74F5074 and related part types represent state-of-the-art TTL technology. After determining the T0 and t of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74F50729 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74F50109 10 nanoseconds after the clock edge. He simply plugs his number into the equation below: MTBF = e(t'/t)/ TofCfI In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (t' < h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying fI by fC gives an answer of 1015 Hz2. From Fig. 4 it is clear that the MTBF is greater than 1010 seconds. Using the above formula MTBF is 1.51 X 1010 seconds or about 480 years.
VCC = Pin 16 GND = Pin 8
SF00601
DESCRIPTION
The 74F50109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for guaranteed propagation delays. The JK design allows operation as a D flip-flop by tying J and K inputs together. The 74F50109 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50109 are: 135ps and 9.8 X 106 sec where represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state.
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term 'metastable immune' to describe characteristics of some of the products in its FAST family. Specifically the 74F50XXX family presently consist of 4 products which displays metastable immune characteristics. This term means that the outputs will not glitch or display an output anomaly under any circumstances including setup and hold time violations. This claim is easily verified on the 74F5074. By running two independent signal generators (see Fig. 1) at nearly the same frequency (in this case 10MHz clock and 10.02 MHz data) the
SIGNAL GENERATOR D Q TRIGGER DIGITAL SCOPE SIGNAL GENERATOR CP Q INPUT
SF00586
Figure 1. Test setup
September 14, 1990
3
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
COMPARISON OF METASTABLE IMMUNE AND NON-IMMUNE CHARACTERISTICS
4
3
2
1
0 Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00602
Figure 2. 74F74 Q output triggered by Q output, Setup and Hold times violated
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00588
Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated
September 14, 1990
4
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t'
106 108 1010 1012 1014 1012 1011 10,000 years 1010 100 years MTBF in seconds 108 one year 107 106 one week 7 8 9 10
SF00589
1015 = fCfI
109
t' in nanoseconds NOTE: VCC = 5V, Tamb = 25C, =135ps, To = 9.8 X 108 sec Figure 4.
TYPICAL VALUES FOR AND T0 AT VARIOUS VCCS AND TEMPERATURES
Tamb = 0C VCC 5.5V 5.0V 4.5V 125ps 115ps 115ps T0 1.0 X 109 sec 1.3 X 1010 sec 3.4 X 1013 sec 138ps 135ps 132ps Tamb = 25C T0 5.4 X 106 sec 9.8 X 106 sec 5.1 X 108 sec 160ps 167ps 175ps Tamb = 70C T0 1.7 X 105 sec 3.9 X 104 sec 7.3 X 104 sec
FUNCTION TABLE
INPUTS SD L H L H H H H H RD H L L H H H H H CP X X X J X X X X h h l l K X X X X l h l h OUTPUTS Q H L H q q H L q Q L H H q q L H q OPERATING MODE Asynchronous set Asynchronous reset Undetermined* Hold Toggle Load "1" (set) Load "0" (reset) Hold 'no change" NOTES: H = High-voltage level h = High-voltage level one setup time prior to low-to-high clock transition L = Low-voltage level l = Low-voltage level one setup time prior to low-to-high clock transition q = Lower case indicate the state of the referenced output prior to the low-to-high clock transition X = Don't care = Low-to-high clock transition = Not low-to-high clock transition * = Both outputs will be high if both SD and RD go low simultaneously
September 14, 1990
5
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA
C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free air temperature range 0 4.5 2.0 0.8 -18 -1 20 +70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA UNIT
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VOH High-level output voltage VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN VIK II IIH IIL IOS Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current current3 Jn, Kn CPn, SDn, RDn Short circuit output VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.5V VCC = MAX -60 IOH = MAX MIN LIMITS TYP2 MAX V 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -250 -20 -150 V V V V A A A A mA UNIT
10%VCC 5%VCC 10%VCC 5%VCC
2.5 2.7
VOL
Low-level output voltage
IOL = MAX
ICC Supply current4 (total) VCC = MAX 22 32 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
September 14, 1990
6
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
AC ELECTRICAL CHARACTERISTICS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION MIN fmax tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn, RDn to Qn or Qn Waveform 1 Waveform 1 Waveform 2 130 2.0 2.0 3.5 3.5 VCC = +5.0V CL = 50pF, RL = 500 TYP 150 3.8 3.8 5.5 5.5 6.0 6.0 8.0 8.0 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 90 2.0 2.0 3.0 3.0 6.5 6.5 8.5 8.5 1.5 UNIT
MAX ns ns ns ns
tsk(o) Output skew1, 2 Waveform 4 1.5 NOTES: 1. | tPN actual - tPM actual| for any output compared to any other output where N and M are either LH or HL. 2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.,).
AC SETUP REQUIREMENTS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION MIN tsu (H) tsu(L) th (H) th (L) tw (H) tw (L) tw (L) trec Setup time, high or low Jn, Kn to CPn Hold time, high or low Jn, Kn to CPn CPn pulse width, high or low SDn or RDn pulse width, low Recovery time SDn or RDn to CP Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 3 1.5 1.5 1.0 1.0 3.0 4.0 3.5 3.0 VCC = +5.0V CL = 50pF, RL = 500 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.0 2.0 1.5 1.5 3.5 5.0 4.0 3.5 UNIT
MAX ns ns ns ns ns
September 14, 1990
7
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
AC WAVEFORMS
Jn, Kn VM tsu(L) VM th(L) 1/fmax CPn RDn VM tw(H) tPLH Qn VM tPHL Qn VM tw(L) VM VM tPLH tPHL Qn VM tPHL tPLH Qn VM VM VM tPLH VM VM VM tPHL VM tsu(H) VM th(H) tw(L) VM tw(L) VM
SDn VM
SF00050 SF00139
Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency
Waveform 2. Propagation delay for set and reset to output, set and reset pulse width
Qn, Qn
VM tsk(o)
SDn or RDn
VM trec Qn, Qn
VM
CPn
VM
SF00590 SF00603
Waveform 4. Output skew
Waveform 3. Recovery time for set or reset to output NOTES: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORM
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
September 14, 1990
8
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1990 Sep 14
9
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1990 Sep 14
10
Philips Semiconductors
Product specification
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
74F50109
NOTES
1990 Sep 14
11
Philips Semiconductors
Product specification
Synchronizing dual J-K positiveedge-triggered flip-flop with metastable immune characteristics
74F50109
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05214
Philips Semiconductors
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